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<section id="a-profile-cpu-architecture-support">
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<span id="arm-emulation"></span><h1>A-profile CPU architecture support<a class="headerlink" href="#a-profile-cpu-architecture-support" title="Link to this heading"></a></h1>
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<p>QEMU’s TCG emulation includes support for the Armv5, Armv6, Armv7 and
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Armv8 versions of the A-profile architecture. It also has support for
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the following architecture extensions:</p>
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<ul class="simple">
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<li><p>FEAT_AA32BF16 (AArch32 BFloat16 instructions)</p></li>
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<li><p>FEAT_AA32HPD (AArch32 hierarchical permission disables)</p></li>
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<li><p>FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions)</p></li>
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<li><p>FEAT_AES (AESD and AESE instructions)</p></li>
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<li><p>FEAT_BBM at level 2 (Translation table break-before-make levels)</p></li>
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<li><p>FEAT_BF16 (AArch64 BFloat16 instructions)</p></li>
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<li><p>FEAT_BTI (Branch Target Identification)</p></li>
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<li><p>FEAT_CRC32 (CRC32 instructions)</p></li>
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<li><p>FEAT_CSV2 (Cache speculation variant 2)</p></li>
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<li><p>FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1)</p></li>
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<li><p>FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)</p></li>
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<li><p>FEAT_CSV2_2 (Cache speculation variant 2, version 2)</p></li>
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<li><p>FEAT_CSV3 (Cache speculation variant 3)</p></li>
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<li><p>FEAT_DGH (Data gathering hint)</p></li>
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<li><p>FEAT_DIT (Data Independent Timing instructions)</p></li>
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<li><p>FEAT_DPB (DC CVAP instruction)</p></li>
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<li><p>FEAT_Debugv8p2 (Debug changes for v8.2)</p></li>
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<li><p>FEAT_Debugv8p4 (Debug changes for v8.4)</p></li>
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<li><p>FEAT_DotProd (Advanced SIMD dot product instructions)</p></li>
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<li><p>FEAT_DoubleFault (Double Fault Extension)</p></li>
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<li><p>FEAT_E0PD (Preventing EL0 access to halves of address maps)</p></li>
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<li><p>FEAT_EPAC (Enhanced pointer authentication)</p></li>
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<li><p>FEAT_ETS (Enhanced Translation Synchronization)</p></li>
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<li><p>FEAT_EVT (Enhanced Virtualization Traps)</p></li>
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<li><p>FEAT_FCMA (Floating-point complex number instructions)</p></li>
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<li><p>FEAT_FGT (Fine-Grained Traps)</p></li>
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<li><p>FEAT_FHM (Floating-point half-precision multiplication instructions)</p></li>
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<li><p>FEAT_FP16 (Half-precision floating-point data processing)</p></li>
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<li><p>FEAT_FPAC (Faulting on AUT* instructions)</p></li>
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<li><p>FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions)</p></li>
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<li><p>FEAT_FRINTTS (Floating-point to integer instructions)</p></li>
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<li><p>FEAT_FlagM (Flag manipulation instructions v2)</p></li>
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<li><p>FEAT_FlagM2 (Enhancements to flag manipulation instructions)</p></li>
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<li><p>FEAT_GTG (Guest translation granule size)</p></li>
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<li><p>FEAT_HAFDBS (Hardware management of the access flag and dirty bit state)</p></li>
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<li><p>FEAT_HBC (Hinted conditional branches)</p></li>
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<li><p>FEAT_HCX (Support for the HCRX_EL2 register)</p></li>
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<li><p>FEAT_HPDS (Hierarchical permission disables)</p></li>
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<li><p>FEAT_HPDS2 (Translation table page-based hardware attributes)</p></li>
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<li><p>FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero)</p></li>
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<li><p>FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)</p></li>
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<li><p>FEAT_IDST (ID space trap handling)</p></li>
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<li><p>FEAT_IESB (Implicit error synchronization event)</p></li>
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<li><p>FEAT_JSCVT (JavaScript conversion instructions)</p></li>
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<li><p>FEAT_LOR (Limited ordering regions)</p></li>
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<li><p>FEAT_LPA (Large Physical Address space)</p></li>
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<li><p>FEAT_LPA2 (Large Physical and virtual Address space v2)</p></li>
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<li><p>FEAT_LRCPC (Load-acquire RCpc instructions)</p></li>
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<li><p>FEAT_LRCPC2 (Load-acquire RCpc instructions v2)</p></li>
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<li><p>FEAT_LSE (Large System Extensions)</p></li>
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<li><p>FEAT_LSE2 (Large System Extensions v2)</p></li>
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<li><p>FEAT_LVA (Large Virtual Address space)</p></li>
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<li><p>FEAT_MOPS (Standardization of memory operations)</p></li>
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<li><p>FEAT_MTE (Memory Tagging Extension)</p></li>
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<li><p>FEAT_MTE2 (Memory Tagging Extension)</p></li>
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<li><p>FEAT_MTE3 (MTE Asymmetric Fault Handling)</p></li>
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<li><p>FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm)</p></li>
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<li><p>FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm)</p></li>
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<li><p>FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm)</p></li>
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<li><p>FEAT_PAN (Privileged access never)</p></li>
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<li><p>FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN)</p></li>
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<li><p>FEAT_PAN3 (Support for SCTLR_ELx.EPAN)</p></li>
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<li><p>FEAT_PAuth (Pointer authentication)</p></li>
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<li><p>FEAT_PAuth2 (Enhancements to pointer authentication)</p></li>
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<li><p>FEAT_PMULL (PMULL, PMULL2 instructions)</p></li>
|
||
<li><p>FEAT_PMUv3p1 (PMU Extensions v3.1)</p></li>
|
||
<li><p>FEAT_PMUv3p4 (PMU Extensions v3.4)</p></li>
|
||
<li><p>FEAT_PMUv3p5 (PMU Extensions v3.5)</p></li>
|
||
<li><p>FEAT_RAS (Reliability, availability, and serviceability)</p></li>
|
||
<li><p>FEAT_RASv1p1 (RAS Extension v1.1)</p></li>
|
||
<li><p>FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions)</p></li>
|
||
<li><p>FEAT_RME (Realm Management Extension) (NB: support status in QEMU is experimental)</p></li>
|
||
<li><p>FEAT_RNG (Random number generator)</p></li>
|
||
<li><p>FEAT_S2FWB (Stage 2 forced Write-Back)</p></li>
|
||
<li><p>FEAT_SB (Speculation Barrier)</p></li>
|
||
<li><p>FEAT_SEL2 (Secure EL2)</p></li>
|
||
<li><p>FEAT_SHA1 (SHA1 instructions)</p></li>
|
||
<li><p>FEAT_SHA256 (SHA256 instructions)</p></li>
|
||
<li><p>FEAT_SHA3 (Advanced SIMD SHA3 instructions)</p></li>
|
||
<li><p>FEAT_SHA512 (Advanced SIMD SHA512 instructions)</p></li>
|
||
<li><p>FEAT_SM3 (Advanced SIMD SM3 instructions)</p></li>
|
||
<li><p>FEAT_SM4 (Advanced SIMD SM4 instructions)</p></li>
|
||
<li><p>FEAT_SME (Scalable Matrix Extension)</p></li>
|
||
<li><p>FEAT_SME_FA64 (Full A64 instruction set in Streaming SVE mode)</p></li>
|
||
<li><p>FEAT_SME_F64F64 (Double-precision floating-point outer product instructions)</p></li>
|
||
<li><p>FEAT_SME_I16I64 (16-bit to 64-bit integer widening outer product instructions)</p></li>
|
||
<li><p>FEAT_SPECRES (Speculation restriction instructions)</p></li>
|
||
<li><p>FEAT_SSBS (Speculative Store Bypass Safe)</p></li>
|
||
<li><p>FEAT_TIDCP1 (EL0 use of IMPLEMENTATION DEFINED functionality)</p></li>
|
||
<li><p>FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)</p></li>
|
||
<li><p>FEAT_TLBIRANGE (TLB invalidate range instructions)</p></li>
|
||
<li><p>FEAT_TTCNP (Translation table Common not private translations)</p></li>
|
||
<li><p>FEAT_TTL (Translation Table Level)</p></li>
|
||
<li><p>FEAT_TTST (Small translation tables)</p></li>
|
||
<li><p>FEAT_UAO (Unprivileged Access Override control)</p></li>
|
||
<li><p>FEAT_VHE (Virtualization Host Extensions)</p></li>
|
||
<li><p>FEAT_VMID16 (16-bit VMID)</p></li>
|
||
<li><p>FEAT_XNX (Translation table stage 2 Unprivileged Execute-never)</p></li>
|
||
<li><p>SVE (The Scalable Vector Extension)</p></li>
|
||
<li><p>SVE2 (The Scalable Vector Extension v2)</p></li>
|
||
</ul>
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<p>For information on the specifics of these extensions, please refer
|
||
to the <a class="reference external" href="https://developer.arm.com/documentation/ddi0487/latest">Armv8-A Arm Architecture Reference Manual</a>.</p>
|
||
<p>When a specific named CPU is being emulated, only those features which
|
||
are present in hardware for that CPU are emulated. (If a feature is
|
||
not in the list above then it is not supported, even if the real
|
||
hardware should have it.) The <code class="docutils literal notranslate"><span class="pre">max</span></code> CPU enables all features.</p>
|
||
</section>
|
||
<section id="r-profile-cpu-architecture-support">
|
||
<h1>R-profile CPU architecture support<a class="headerlink" href="#r-profile-cpu-architecture-support" title="Link to this heading"></a></h1>
|
||
<p>QEMU’s TCG emulation support for R-profile CPUs is currently limited.
|
||
We emulate only the Cortex-R5 and Cortex-R5F CPUs.</p>
|
||
</section>
|
||
<section id="m-profile-cpu-architecture-support">
|
||
<h1>M-profile CPU architecture support<a class="headerlink" href="#m-profile-cpu-architecture-support" title="Link to this heading"></a></h1>
|
||
<p>QEMU’s TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and
|
||
Armv8.1-M versions of the M-profile architucture. It also has support
|
||
for the following architecture extensions:</p>
|
||
<ul class="simple">
|
||
<li><p>FP (Floating-point Extension)</p></li>
|
||
<li><p>FPCXT (FPCXT access instructions)</p></li>
|
||
<li><p>HP (Half-precision floating-point instructions)</p></li>
|
||
<li><p>LOB (Low Overhead loops and Branch future)</p></li>
|
||
<li><p>M (Main Extension)</p></li>
|
||
<li><p>MPU (Memory Protection Unit Extension)</p></li>
|
||
<li><p>PXN (Privileged Execute Never)</p></li>
|
||
<li><p>RAS (Reliability, Serviceability and Availability): “minimum RAS Extension” only</p></li>
|
||
<li><p>S (Security Extension)</p></li>
|
||
<li><p>ST (System Timer Extension)</p></li>
|
||
</ul>
|
||
<p>For information on the specifics of these extensions, please refer
|
||
to the <a class="reference external" href="https://developer.arm.com/documentation/ddi0553/latest">Armv8-M Arm Architecture Reference Manual</a>.</p>
|
||
<p>When a specific named CPU is being emulated, only those features which
|
||
are present in hardware for that CPU are emulated. (If a feature is
|
||
not in the list above then it is not supported, even if the real
|
||
hardware should have it.) There is no equivalent of the <code class="docutils literal notranslate"><span class="pre">max</span></code> CPU for
|
||
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