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<section id="compute-express-link-cxl">
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<h1>Compute Express Link (CXL)<a class="headerlink" href="#compute-express-link-cxl" title="Link to this heading"></a></h1>
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<p>From the view of a single host, CXL is an interconnect standard that
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targets accelerators and memory devices attached to a CXL host.
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This description will focus on those aspects visible either to
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software running on a QEMU emulated host or to the internals of
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functional emulation. As such, it will skip over many of the
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electrical and protocol elements that would be more of interest
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for real hardware and will dominate more general introductions to CXL.
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It will also completely ignore the fabric management aspects of CXL
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by considering only a single host and a static configuration.</p>
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<p>CXL shares many concepts and much of the infrastructure of PCI Express,
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with CXL Host Bridges, which have CXL Root Ports which may be directly
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attached to CXL or PCI End Points. Alternatively there may be CXL Switches
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with CXL and PCI Endpoints attached below them. In many cases additional
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control and capabilities are exposed via PCI Express interfaces.
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This sharing of interfaces and hence emulation code is reflected
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in how the devices are emulated in QEMU. In most cases the various
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CXL elements are built upon an equivalent PCIe devices.</p>
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<p>CXL devices support the following interfaces:</p>
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<ul class="simple">
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<li><p>Most conventional PCIe interfaces</p>
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<ul>
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<li><p>Configuration space access</p></li>
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<li><p>BAR mapped memory accesses used for registers and mailboxes.</p></li>
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<li><p>MSI/MSI-X</p></li>
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<li><p>AER</p></li>
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<li><p>DOE mailboxes</p></li>
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<li><p>IDE</p></li>
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<li><p>Many other PCI express defined interfaces..</p></li>
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</ul>
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</li>
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<li><p>Memory operations</p>
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<ul>
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<li><p>Equivalent of accessing DRAM / NVDIMMs. Any access / feature
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supported by the host for normal memory should also work for
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CXL attached memory devices.</p></li>
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</ul>
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</li>
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<li><p>Cache operations. The are mostly irrelevant to QEMU emulation as
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QEMU is not emulating a coherency protocol. Any emulation related
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to these will be device specific and is out of the scope of this
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document.</p></li>
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</ul>
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<section id="cxl-2-0-device-types">
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<h2>CXL 2.0 Device Types<a class="headerlink" href="#cxl-2-0-device-types" title="Link to this heading"></a></h2>
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<p>CXL 2.0 End Points are often categorized into three types.</p>
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<p><strong>Type 1:</strong> These support coherent caching of host memory. Example might
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be a crypto accelerators. May also have device private memory accessible
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via means such as PCI memory reads and writes to BARs.</p>
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<p><strong>Type 2:</strong> These support coherent caching of host memory and host
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managed device memory (HDM) for which the coherency protocol is managed
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by the host. This is a complex topic, so for more information on CXL
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coherency see the CXL 2.0 specification.</p>
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<p><strong>Type 3 Memory devices:</strong> These devices act as a means of attaching
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additional memory (HDM) to a CXL host including both volatile and
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persistent memory. The CXL topology may support interleaving across a
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number of Type 3 memory devices using HDM Decoders in the host, host
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bridge, switch upstream port and endpoints.</p>
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</section>
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<section id="scope-of-cxl-emulation-in-qemu">
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<h2>Scope of CXL emulation in QEMU<a class="headerlink" href="#scope-of-cxl-emulation-in-qemu" title="Link to this heading"></a></h2>
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<p>The focus of CXL emulation is CXL revision 2.0 and later. Earlier CXL
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revisions defined a smaller set of features, leaving much of the control
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interface as implementation defined or device specific, making generic
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emulation challenging with host specific firmware being responsible
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for setup and the Endpoints being presented to operating systems
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as Root Complex Integrated End Points. CXL rev 2.0 looks a lot
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more like PCI Express, with fully specified discoverability
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of the CXL topology.</p>
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</section>
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<section id="cxl-system-components">
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<h2>CXL System components<a class="headerlink" href="#cxl-system-components" title="Link to this heading"></a></h2>
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<p>A CXL system is made up a Host with a number of ‘standard components’
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the control and capabilities of which are discoverable by system software
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using means described in the CXL 2.0 specification.</p>
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<section id="cxl-fixed-memory-windows-cfmw">
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<h3>CXL Fixed Memory Windows (CFMW)<a class="headerlink" href="#cxl-fixed-memory-windows-cfmw" title="Link to this heading"></a></h3>
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<p>A CFMW consists of a particular range of Host Physical Address space
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which is routed to particular CXL Host Bridges. At time of generic
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software initialization it will have a particularly interleaving
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configuration and associated Quality of Service Throttling Group (QTG).
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This information is available to system software, when making
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decisions about how to configure interleave across available CXL
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memory devices. It is provide as CFMW Structures (CFMWS) in
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the CXL Early Discovery Table, an ACPI table.</p>
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<p>Note: QTG 0 is the only one currently supported in QEMU.</p>
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</section>
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<section id="cxl-host-bridge-cxl-hb">
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<h3>CXL Host Bridge (CXL HB)<a class="headerlink" href="#cxl-host-bridge-cxl-hb" title="Link to this heading"></a></h3>
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<p>A CXL host bridge is similar to the PCIe equivalent, but with a
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specification defined register interface called CXL Host Bridge
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Component Registers (CHBCR). The location of this CHBCR MMIO
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space is described to system software via a CXL Host Bridge
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Structure (CHBS) in the CEDT ACPI table. The actual interfaces
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are identical to those used for other parts of the CXL hierarchy
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as CXL Component Registers in PCI BARs.</p>
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<p>Interfaces provided include:</p>
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<ul class="simple">
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<li><p>Configuration of HDM Decoders to route CXL Memory accesses with
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a particularly Host Physical Address range to the target port
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below which the CXL device servicing that address lies. This
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may be a mapping to a single Root Port (RP) or across a set of
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target RPs.</p></li>
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</ul>
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</section>
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<section id="cxl-root-ports-cxl-rp">
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<h3>CXL Root Ports (CXL RP)<a class="headerlink" href="#cxl-root-ports-cxl-rp" title="Link to this heading"></a></h3>
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||
<p>A CXL Root Port serves the same purpose as a PCIe Root Port.
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||
There are a number of CXL specific Designated Vendor Specific
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||
Extended Capabilities (DVSEC) in PCIe Configuration Space
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||
and associated component register access via PCI bars.</p>
|
||
</section>
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||
<section id="cxl-switch">
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||
<h3>CXL Switch<a class="headerlink" href="#cxl-switch" title="Link to this heading"></a></h3>
|
||
<p>Here we consider a simple CXL switch with only a single
|
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virtual hierarchy. Whilst more complex devices exist, their
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||
visibility to a particular host is generally the same as for
|
||
a simple switch design. Hosts often have no awareness
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||
of complex rerouting and device pooling, they simply see
|
||
devices being hot added or hot removed.</p>
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||
<p>A CXL switch has a similar architecture to those in PCIe,
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||
with a single upstream port, internal PCI bus and multiple
|
||
downstream ports.</p>
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||
<p>Both the CXL upstream and downstream ports have CXL specific
|
||
DVSECs in configuration space, and component registers in PCI
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||
BARs. The Upstream Port has the configuration interfaces for
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||
the HDM decoders which route incoming memory accesses to the
|
||
appropriate downstream port.</p>
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||
<p>A CXL switch is created in a similar fashion to PCI switches
|
||
by creating an upstream port (cxl-upstream) and a number of
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downstream ports on the internal switch bus (cxl-downstream).</p>
|
||
</section>
|
||
<section id="cxl-memory-devices-type-3">
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||
<h3>CXL Memory Devices - Type 3<a class="headerlink" href="#cxl-memory-devices-type-3" title="Link to this heading"></a></h3>
|
||
<p>CXL type 3 devices use a PCI class code and are intended to be supported
|
||
by a generic operating system driver. They have HDM decoders
|
||
though in these EP devices, the decoder is responsible not for
|
||
routing but for translation of the incoming host physical address (HPA)
|
||
into a Device Physical Address (DPA).</p>
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||
</section>
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||
</section>
|
||
<section id="cxl-memory-interleave">
|
||
<h2>CXL Memory Interleave<a class="headerlink" href="#cxl-memory-interleave" title="Link to this heading"></a></h2>
|
||
<p>To understand the interaction of different CXL hardware components which
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||
are emulated in QEMU, let us consider a memory read in a fully configured
|
||
CXL topology. Note that system software is responsible for configuration
|
||
of all components with the exception of the CFMWs. System software is
|
||
responsible for allocating appropriate ranges from within the CFMWs
|
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and exposing those via normal memory configurations as would be done
|
||
for system RAM.</p>
|
||
<p>Example system topology. x marks the match in each decoder level:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">|<------------------</span><span class="n">SYSTEM</span> <span class="n">PHYSICAL</span> <span class="n">ADDRESS</span> <span class="n">MAP</span> <span class="p">(</span><span class="mi">1</span><span class="p">)</span><span class="o">----------------->|</span>
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<span class="o">|</span> <span class="n">__________</span> <span class="n">__________________________________</span> <span class="n">__________</span> <span class="o">|</span>
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<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
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<span class="o">|</span> <span class="o">|</span> <span class="n">CFMW</span> <span class="mi">0</span> <span class="o">|</span> <span class="o">|</span> <span class="n">CXL</span> <span class="n">Fixed</span> <span class="n">Memory</span> <span class="n">Window</span> <span class="mi">1</span> <span class="o">|</span> <span class="o">|</span> <span class="n">CFMW</span> <span class="mi">2</span> <span class="o">|</span> <span class="o">|</span>
|
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<span class="o">|</span> <span class="o">|</span> <span class="n">HB0</span> <span class="n">only</span> <span class="o">|</span> <span class="o">|</span> <span class="n">Configured</span> <span class="n">to</span> <span class="n">interleave</span> <span class="n">memory</span> <span class="o">|</span> <span class="o">|</span> <span class="n">HB1</span> <span class="n">only</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="n">memory</span> <span class="n">accesses</span> <span class="n">across</span> <span class="n">HB0</span><span class="o">/</span><span class="n">HB1</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span><span class="n">__________</span><span class="o">|</span> <span class="o">|</span><span class="n">_____x____________________________</span><span class="o">|</span> <span class="o">|</span><span class="n">__________</span><span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">Interleave</span> <span class="n">Decoder</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">Matches</span> <span class="n">this</span> <span class="n">HB</span> <span class="o">|</span> <span class="o">|</span>
|
||
\<span class="n">_____________</span><span class="o">|</span> <span class="o">|</span><span class="n">_____________</span><span class="o">/</span>
|
||
<span class="n">__________</span><span class="o">|</span><span class="n">__________</span> <span class="n">_____</span><span class="o">|</span><span class="n">_______________</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="p">(</span><span class="mi">2</span><span class="p">)</span> <span class="o">|</span> <span class="n">CXL</span> <span class="n">HB</span> <span class="mi">0</span> <span class="o">|</span> <span class="o">|</span> <span class="n">CXL</span> <span class="n">HB</span> <span class="mi">1</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">HB</span> <span class="n">IntLv</span> <span class="n">Decoders</span> <span class="o">|</span> <span class="o">|</span> <span class="n">HB</span> <span class="n">IntLv</span> <span class="n">Decoders</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">PCI</span><span class="o">/</span><span class="n">CXL</span> <span class="n">Root</span> <span class="n">Bus</span> <span class="mi">0</span><span class="n">c</span> <span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span><span class="o">/</span><span class="n">CXL</span> <span class="n">Root</span> <span class="n">Bus</span> <span class="mi">0</span><span class="n">d</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span><span class="n">___x_________________</span><span class="o">|</span> <span class="o">|</span><span class="n">_____________________</span><span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="n">A</span> <span class="n">HB</span> <span class="mi">0</span> <span class="n">HDM</span> <span class="n">Decoder</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="n">matches</span> <span class="n">this</span> <span class="n">Port</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="n">___________</span><span class="o">|</span><span class="n">___</span> <span class="n">__________</span><span class="o">|</span><span class="n">__</span> <span class="n">__</span><span class="o">|</span><span class="n">_________</span> <span class="n">___</span><span class="o">|</span><span class="n">_________</span>
|
||
<span class="p">(</span><span class="mi">3</span><span class="p">)</span><span class="o">|</span> <span class="n">Root</span> <span class="n">Port</span> <span class="mi">0</span> <span class="o">|</span> <span class="o">|</span> <span class="n">Root</span> <span class="n">Port</span> <span class="mi">1</span> <span class="o">|</span> <span class="o">|</span> <span class="n">Root</span> <span class="n">Port</span> <span class="mi">2</span><span class="o">|</span> <span class="o">|</span> <span class="n">Root</span> <span class="n">Port</span> <span class="mi">3</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">Appears</span> <span class="ow">in</span> <span class="o">|</span> <span class="o">|</span> <span class="n">Appears</span> <span class="ow">in</span> <span class="o">|</span> <span class="o">|</span> <span class="n">Appears</span> <span class="ow">in</span> <span class="o">|</span> <span class="o">|</span> <span class="n">Appear</span> <span class="ow">in</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">PCI</span> <span class="n">topology</span> <span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span> <span class="n">topology</span><span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span> <span class="n">topo</span> <span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span> <span class="n">topo</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="k">as</span> <span class="mi">0</span><span class="n">c</span><span class="p">:</span><span class="mf">00.0</span> <span class="o">|</span> <span class="o">|</span> <span class="k">as</span> <span class="mi">0</span><span class="n">c</span><span class="p">:</span><span class="mf">01.0</span> <span class="o">|</span> <span class="o">|</span> <span class="k">as</span> <span class="n">de</span><span class="p">:</span><span class="mf">00.0</span> <span class="o">|</span> <span class="o">|</span> <span class="k">as</span> <span class="n">de</span><span class="p">:</span><span class="mf">01.0</span> <span class="o">|</span>
|
||
<span class="o">|</span><span class="n">_______________</span><span class="o">|</span> <span class="o">|</span><span class="n">_____________</span><span class="o">|</span> <span class="o">|</span><span class="n">____________</span><span class="o">|</span> <span class="o">|</span><span class="n">_____________</span><span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="n">_____</span><span class="o">|</span><span class="n">_________</span> <span class="n">______</span><span class="o">|</span><span class="n">______</span> <span class="n">______</span><span class="o">|</span><span class="n">_____</span> <span class="n">______</span><span class="o">|</span><span class="n">_______</span>
|
||
<span class="p">(</span><span class="mi">4</span><span class="p">)</span><span class="o">|</span> <span class="n">x</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">CXL</span> <span class="n">Type3</span> <span class="mi">0</span> <span class="o">|</span> <span class="o">|</span> <span class="n">CXL</span> <span class="n">Type3</span> <span class="mi">1</span> <span class="o">|</span> <span class="o">|</span> <span class="n">CXL</span> <span class="n">type3</span> <span class="mi">2</span><span class="o">|</span> <span class="o">|</span> <span class="n">CLX</span> <span class="n">Type</span> <span class="mi">3</span> <span class="mi">3</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">PMEM0</span><span class="p">(</span><span class="n">Vol</span> <span class="n">LSA</span><span class="p">)</span><span class="o">|</span> <span class="o">|</span> <span class="n">PMEM1</span> <span class="p">(</span><span class="o">...</span><span class="p">)</span> <span class="o">|</span> <span class="o">|</span> <span class="n">PMEM2</span> <span class="p">(</span><span class="o">...</span><span class="p">)</span><span class="o">|</span> <span class="o">|</span> <span class="n">PMEM3</span> <span class="p">(</span><span class="o">...</span><span class="p">)</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">Decoder</span> <span class="n">to</span> <span class="n">go</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="kn">from</span> <span class="nn">host</span> <span class="n">PA</span> <span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span> <span class="mi">0</span><span class="n">e</span><span class="p">:</span><span class="mf">00.0</span> <span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span> <span class="n">df</span><span class="p">:</span><span class="mf">00.0</span><span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span> <span class="n">e0</span><span class="p">:</span><span class="mf">00.0</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">to</span> <span class="n">device</span> <span class="n">PA</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">PCI</span> <span class="k">as</span> <span class="mi">0</span><span class="n">d</span><span class="p">:</span><span class="mf">00.0</span><span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span><span class="n">_______________</span><span class="o">|</span> <span class="o">|</span><span class="n">_____________</span><span class="o">|</span> <span class="o">|</span><span class="n">____________</span><span class="o">|</span> <span class="o">|</span><span class="n">______________</span><span class="o">|</span>
|
||
</pre></div>
|
||
</div>
|
||
<p>Notes:</p>
|
||
<ol class="arabic simple">
|
||
<li><p><strong>3 CXL Fixed Memory Windows (CFMW)</strong> corresponding to different
|
||
ranges of the system physical address map. Each CFMW has
|
||
particular interleave setup across the CXL Host Bridges (HB)
|
||
CFMW0 provides uninterleaved access to HB0, CFMW2 provides
|
||
uninterleaved access to HB1. CFMW1 provides interleaved memory access
|
||
across HB0 and HB1.</p></li>
|
||
<li><p><strong>Two CXL Host Bridges</strong>. Each of these has 2 CXL Root Ports and
|
||
programmable HDM decoders to route memory accesses either to
|
||
a single port or interleave them across multiple ports.
|
||
A complex configuration here, might be to use the following HDM
|
||
decoders in HB0. HDM0 routes CFMW0 requests to RP0 and hence
|
||
part of CXL Type3 0. HDM1 routes CFMW0 requests from a
|
||
different region of the CFMW0 PA range to RP2 and hence part
|
||
of CXL Type 3 1. HDM2 routes yet another PA range from within
|
||
CFMW0 to be interleaved across RP0 and RP1, providing 2 way
|
||
interleave of part of the memory provided by CXL Type3 0 and
|
||
CXL Type 3 1. HDM3 routes those interleaved accesses from
|
||
CFMW1 that target HB0 to RP 0 and another part of the memory of
|
||
CXL Type 3 0 (as part of a 2 way interleave at the system level
|
||
across for example CXL Type3 0 and CXL Type3 2.
|
||
HDM4 is used to enable system wide 4 way interleave across all
|
||
the present CXL type3 devices, by interleaving those (interleaved)
|
||
requests that HB0 receives from from CFMW1 across RP 0 and
|
||
RP 1 and hence to yet more regions of the memory of the
|
||
attached Type3 devices. Note this is a representative subset
|
||
of the full range of possible HDM decoder configurations in this
|
||
topology.</p></li>
|
||
<li><p><strong>Four CXL Root Ports.</strong> In this case the CXL Type 3 devices are
|
||
directly attached to these ports.</p></li>
|
||
<li><p><strong>Four CXL Type3 memory expansion devices.</strong> These will each have
|
||
HDM decoders, but in this case rather than performing interleave
|
||
they will take the Host Physical Addresses of accesses and map
|
||
them to their own local Device Physical Address Space (DPA).</p></li>
|
||
</ol>
|
||
<p>Example topology involving a switch:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">|<------------------</span><span class="n">SYSTEM</span> <span class="n">PHYSICAL</span> <span class="n">ADDRESS</span> <span class="n">MAP</span> <span class="p">(</span><span class="mi">1</span><span class="p">)</span><span class="o">----------------->|</span>
|
||
<span class="o">|</span> <span class="n">__________</span> <span class="n">__________________________________</span> <span class="n">__________</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="n">CFMW</span> <span class="mi">0</span> <span class="o">|</span> <span class="o">|</span> <span class="n">CXL</span> <span class="n">Fixed</span> <span class="n">Memory</span> <span class="n">Window</span> <span class="mi">1</span> <span class="o">|</span> <span class="o">|</span> <span class="n">CFMW</span> <span class="mi">2</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="n">HB0</span> <span class="n">only</span> <span class="o">|</span> <span class="o">|</span> <span class="n">Configured</span> <span class="n">to</span> <span class="n">interleave</span> <span class="n">memory</span> <span class="o">|</span> <span class="o">|</span> <span class="n">HB1</span> <span class="n">only</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="n">memory</span> <span class="n">accesses</span> <span class="n">across</span> <span class="n">HB0</span><span class="o">/</span><span class="n">HB1</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span><span class="n">____x_____</span><span class="o">|</span> <span class="o">|</span><span class="n">__________________________________</span><span class="o">|</span> <span class="o">|</span><span class="n">__________</span><span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="n">Interleave</span> <span class="n">Decoder</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="n">Matches</span> <span class="n">this</span> <span class="n">HB</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
\<span class="n">_____________</span><span class="o">|</span> <span class="o">|</span><span class="n">_____________</span><span class="o">/</span>
|
||
<span class="n">__________</span><span class="o">|</span><span class="n">__________</span> <span class="n">_____</span><span class="o">|</span><span class="n">_______________</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">CXL</span> <span class="n">HB</span> <span class="mi">0</span> <span class="o">|</span> <span class="o">|</span> <span class="n">CXL</span> <span class="n">HB</span> <span class="mi">1</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">HB</span> <span class="n">IntLv</span> <span class="n">Decoders</span> <span class="o">|</span> <span class="o">|</span> <span class="n">HB</span> <span class="n">IntLv</span> <span class="n">Decoders</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">PCI</span><span class="o">/</span><span class="n">CXL</span> <span class="n">Root</span> <span class="n">Bus</span> <span class="mi">0</span><span class="n">c</span> <span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span><span class="o">/</span><span class="n">CXL</span> <span class="n">Root</span> <span class="n">Bus</span> <span class="mi">0</span><span class="n">d</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span><span class="n">___x_________________</span><span class="o">|</span> <span class="o">|</span><span class="n">_____________________</span><span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span>
|
||
<span class="n">A</span> <span class="n">HB</span> <span class="mi">0</span> <span class="n">HDM</span> <span class="n">Decoder</span>
|
||
<span class="n">matches</span> <span class="n">this</span> <span class="n">Port</span>
|
||
<span class="n">___________</span><span class="o">|</span><span class="n">___</span>
|
||
<span class="o">|</span> <span class="n">Root</span> <span class="n">Port</span> <span class="mi">0</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">Appears</span> <span class="ow">in</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">PCI</span> <span class="n">topology</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="k">as</span> <span class="mi">0</span><span class="n">c</span><span class="p">:</span><span class="mf">00.0</span> <span class="o">|</span>
|
||
<span class="o">|</span><span class="n">___________x___</span><span class="o">|</span>
|
||
<span class="o">|</span>
|
||
<span class="o">|</span>
|
||
\<span class="n">_____________________</span>
|
||
<span class="o">|</span>
|
||
<span class="o">|</span>
|
||
<span class="o">---------------------------------------------------</span>
|
||
<span class="o">|</span> <span class="n">Switch</span> <span class="mi">0</span> <span class="n">USP</span> <span class="k">as</span> <span class="n">PCI</span> <span class="mi">0</span><span class="n">d</span><span class="p">:</span><span class="mf">00.0</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">USP</span> <span class="n">has</span> <span class="n">HDM</span> <span class="n">decoder</span> <span class="n">which</span> <span class="n">direct</span> <span class="n">traffic</span> <span class="n">to</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">appropriate</span> <span class="n">downstream</span> <span class="n">port</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">Switch</span> <span class="n">BUS</span> <span class="n">appears</span> <span class="k">as</span> <span class="mi">0</span><span class="n">e</span> <span class="o">|</span>
|
||
<span class="o">|</span><span class="n">x__________________________________________________</span><span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="n">_____</span><span class="o">|</span><span class="n">_________</span> <span class="n">______</span><span class="o">|</span><span class="n">______</span> <span class="n">______</span><span class="o">|</span><span class="n">_____</span> <span class="n">______</span><span class="o">|</span><span class="n">_______</span>
|
||
<span class="p">(</span><span class="mi">4</span><span class="p">)</span><span class="o">|</span> <span class="n">x</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">CXL</span> <span class="n">Type3</span> <span class="mi">0</span> <span class="o">|</span> <span class="o">|</span> <span class="n">CXL</span> <span class="n">Type3</span> <span class="mi">1</span> <span class="o">|</span> <span class="o">|</span> <span class="n">CXL</span> <span class="n">type3</span> <span class="mi">2</span><span class="o">|</span> <span class="o">|</span> <span class="n">CLX</span> <span class="n">Type</span> <span class="mi">3</span> <span class="mi">3</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">PMEM0</span><span class="p">(</span><span class="n">Vol</span> <span class="n">LSA</span><span class="p">)</span><span class="o">|</span> <span class="o">|</span> <span class="n">PMEM1</span> <span class="p">(</span><span class="o">...</span><span class="p">)</span> <span class="o">|</span> <span class="o">|</span> <span class="n">PMEM2</span> <span class="p">(</span><span class="o">...</span><span class="p">)</span><span class="o">|</span> <span class="o">|</span> <span class="n">PMEM3</span> <span class="p">(</span><span class="o">...</span><span class="p">)</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">Decoder</span> <span class="n">to</span> <span class="n">go</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="kn">from</span> <span class="nn">host</span> <span class="n">PA</span> <span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span> <span class="mi">10</span><span class="p">:</span><span class="mf">00.0</span> <span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span> <span class="mi">11</span><span class="p">:</span><span class="mf">00.0</span><span class="o">|</span> <span class="o">|</span> <span class="n">PCI</span> <span class="mi">12</span><span class="p">:</span><span class="mf">00.0</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">to</span> <span class="n">device</span> <span class="n">PA</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span> <span class="n">PCI</span> <span class="k">as</span> <span class="mi">0</span><span class="n">f</span><span class="p">:</span><span class="mf">00.0</span><span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span> <span class="o">|</span>
|
||
<span class="o">|</span><span class="n">_______________</span><span class="o">|</span> <span class="o">|</span><span class="n">_____________</span><span class="o">|</span> <span class="o">|</span><span class="n">____________</span><span class="o">|</span> <span class="o">|</span><span class="n">______________</span><span class="o">|</span>
|
||
</pre></div>
|
||
</div>
|
||
</section>
|
||
<section id="example-command-lines">
|
||
<h2>Example command lines<a class="headerlink" href="#example-command-lines" title="Link to this heading"></a></h2>
|
||
<p>A very simple setup with just one directly attached CXL Type 3 Persistent Memory device:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">qemu</span><span class="o">-</span><span class="n">system</span><span class="o">-</span><span class="n">x86_64</span> <span class="o">-</span><span class="n">M</span> <span class="n">q35</span><span class="p">,</span><span class="n">cxl</span><span class="o">=</span><span class="n">on</span> <span class="o">-</span><span class="n">m</span> <span class="mi">4</span><span class="n">G</span><span class="p">,</span><span class="n">maxmem</span><span class="o">=</span><span class="mi">8</span><span class="n">G</span><span class="p">,</span><span class="n">slots</span><span class="o">=</span><span class="mi">8</span> <span class="o">-</span><span class="n">smp</span> <span class="mi">4</span> \
|
||
<span class="o">...</span>
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem1</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">cxltest</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa1</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">lsa</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">pxb</span><span class="o">-</span><span class="n">cxl</span><span class="p">,</span><span class="n">bus_nr</span><span class="o">=</span><span class="mi">12</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">pcie</span><span class="mf">.0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">rp</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">root_port13</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">2</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">root_port13</span><span class="p">,</span><span class="n">persistent</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem1</span><span class="p">,</span><span class="n">lsa</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa1</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">pmem0</span> \
|
||
<span class="o">-</span><span class="n">M</span> <span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">targets</span><span class="mf">.0</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">size</span><span class="o">=</span><span class="mi">4</span><span class="n">G</span>
|
||
</pre></div>
|
||
</div>
|
||
<p>A very simple setup with just one directly attached CXL Type 3 Volatile Memory device:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">qemu</span><span class="o">-</span><span class="n">system</span><span class="o">-</span><span class="n">x86_64</span> <span class="o">-</span><span class="n">M</span> <span class="n">q35</span><span class="p">,</span><span class="n">cxl</span><span class="o">=</span><span class="n">on</span> <span class="o">-</span><span class="n">m</span> <span class="mi">4</span><span class="n">G</span><span class="p">,</span><span class="n">maxmem</span><span class="o">=</span><span class="mi">8</span><span class="n">G</span><span class="p">,</span><span class="n">slots</span><span class="o">=</span><span class="mi">8</span> <span class="o">-</span><span class="n">smp</span> <span class="mi">4</span> \
|
||
<span class="o">...</span>
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">ram</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">vmem0</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">pxb</span><span class="o">-</span><span class="n">cxl</span><span class="p">,</span><span class="n">bus_nr</span><span class="o">=</span><span class="mi">12</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">pcie</span><span class="mf">.0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">rp</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">root_port13</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">2</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">root_port13</span><span class="p">,</span><span class="n">volatile</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">vmem0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">vmem0</span> \
|
||
<span class="o">-</span><span class="n">M</span> <span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">targets</span><span class="mf">.0</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">size</span><span class="o">=</span><span class="mi">4</span><span class="n">G</span>
|
||
</pre></div>
|
||
</div>
|
||
<p>The same volatile setup may optionally include an LSA region:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">qemu</span><span class="o">-</span><span class="n">system</span><span class="o">-</span><span class="n">x86_64</span> <span class="o">-</span><span class="n">M</span> <span class="n">q35</span><span class="p">,</span><span class="n">cxl</span><span class="o">=</span><span class="n">on</span> <span class="o">-</span><span class="n">m</span> <span class="mi">4</span><span class="n">G</span><span class="p">,</span><span class="n">maxmem</span><span class="o">=</span><span class="mi">8</span><span class="n">G</span><span class="p">,</span><span class="n">slots</span><span class="o">=</span><span class="mi">8</span> <span class="o">-</span><span class="n">smp</span> <span class="mi">4</span> \
|
||
<span class="o">...</span>
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">ram</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">vmem0</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa0</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">lsa</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">pxb</span><span class="o">-</span><span class="n">cxl</span><span class="p">,</span><span class="n">bus_nr</span><span class="o">=</span><span class="mi">12</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">pcie</span><span class="mf">.0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">rp</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">root_port13</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">2</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">root_port13</span><span class="p">,</span><span class="n">volatile</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">vmem0</span><span class="p">,</span><span class="n">lsa</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">vmem0</span> \
|
||
<span class="o">-</span><span class="n">M</span> <span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">targets</span><span class="mf">.0</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">size</span><span class="o">=</span><span class="mi">4</span><span class="n">G</span>
|
||
</pre></div>
|
||
</div>
|
||
<p>A setup suitable for 4 way interleave. Only one fixed window provided, to enable 2 way
|
||
interleave across 2 CXL host bridges. Each host bridge has 2 CXL Root Ports, with
|
||
the CXL Type3 device directly attached (no switches).:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">qemu</span><span class="o">-</span><span class="n">system</span><span class="o">-</span><span class="n">x86_64</span> <span class="o">-</span><span class="n">M</span> <span class="n">q35</span><span class="p">,</span><span class="n">cxl</span><span class="o">=</span><span class="n">on</span> <span class="o">-</span><span class="n">m</span> <span class="mi">4</span><span class="n">G</span><span class="p">,</span><span class="n">maxmem</span><span class="o">=</span><span class="mi">8</span><span class="n">G</span><span class="p">,</span><span class="n">slots</span><span class="o">=</span><span class="mi">8</span> <span class="o">-</span><span class="n">smp</span> <span class="mi">4</span> \
|
||
<span class="o">...</span>
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem1</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">cxltest</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem2</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">cxltest2</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem3</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">cxltest3</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem4</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">cxltest4</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa1</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">lsa</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa2</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">lsa2</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa3</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">lsa3</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa4</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">lsa4</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">pxb</span><span class="o">-</span><span class="n">cxl</span><span class="p">,</span><span class="n">bus_nr</span><span class="o">=</span><span class="mi">12</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">pcie</span><span class="mf">.0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">pxb</span><span class="o">-</span><span class="n">cxl</span><span class="p">,</span><span class="n">bus_nr</span><span class="o">=</span><span class="mi">222</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">pcie</span><span class="mf">.0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.2</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">rp</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">root_port13</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">2</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">root_port13</span><span class="p">,</span><span class="n">persistent</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem1</span><span class="p">,</span><span class="n">lsa</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa1</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">pmem0</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">rp</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">1</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">root_port14</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">3</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">root_port14</span><span class="p">,</span><span class="n">persistent</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem2</span><span class="p">,</span><span class="n">lsa</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa2</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">pmem1</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">rp</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.2</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">root_port15</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">5</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">root_port15</span><span class="p">,</span><span class="n">persistent</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem3</span><span class="p">,</span><span class="n">lsa</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa3</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">pmem2</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">rp</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">1</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.2</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">root_port16</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">6</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">root_port16</span><span class="p">,</span><span class="n">persistent</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem4</span><span class="p">,</span><span class="n">lsa</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa4</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">pmem3</span> \
|
||
<span class="o">-</span><span class="n">M</span> <span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">targets</span><span class="mf">.0</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">targets</span><span class="mf">.1</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.2</span><span class="p">,</span><span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">size</span><span class="o">=</span><span class="mi">4</span><span class="n">G</span><span class="p">,</span><span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">interleave</span><span class="o">-</span><span class="n">granularity</span><span class="o">=</span><span class="mi">8</span><span class="n">k</span>
|
||
</pre></div>
|
||
</div>
|
||
<p>An example of 4 devices below a switch suitable for 1, 2 or 4 way interleave:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="n">qemu</span><span class="o">-</span><span class="n">system</span><span class="o">-</span><span class="n">x86_64</span> <span class="o">-</span><span class="n">M</span> <span class="n">q35</span><span class="p">,</span><span class="n">cxl</span><span class="o">=</span><span class="n">on</span> <span class="o">-</span><span class="n">m</span> <span class="mi">4</span><span class="n">G</span><span class="p">,</span><span class="n">maxmem</span><span class="o">=</span><span class="mi">8</span><span class="n">G</span><span class="p">,</span><span class="n">slots</span><span class="o">=</span><span class="mi">8</span> <span class="o">-</span><span class="n">smp</span> <span class="mi">4</span> \
|
||
<span class="o">...</span>
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem0</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">cxltest</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem1</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">cxltest1</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem2</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">cxltest2</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem3</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">cxltest3</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa0</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">lsa0</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa1</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">lsa1</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa2</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">lsa2</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">file</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa3</span><span class="p">,</span><span class="n">share</span><span class="o">=</span><span class="n">on</span><span class="p">,</span><span class="n">mem</span><span class="o">-</span><span class="n">path</span><span class="o">=/</span><span class="n">tmp</span><span class="o">/</span><span class="n">lsa3</span><span class="o">.</span><span class="n">raw</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">256</span><span class="n">M</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">pxb</span><span class="o">-</span><span class="n">cxl</span><span class="p">,</span><span class="n">bus_nr</span><span class="o">=</span><span class="mi">12</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">pcie</span><span class="mf">.0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">rp</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">root_port0</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">0</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">rp</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">1</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">root_port1</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">1</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">upstream</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">root_port0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">us0</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">downstream</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">us0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">swport0</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">4</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">swport0</span><span class="p">,</span><span class="n">persistent</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem0</span><span class="p">,</span><span class="n">lsa</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">pmem0</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">downstream</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">1</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">us0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">swport1</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">5</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">swport1</span><span class="p">,</span><span class="n">persistent</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem1</span><span class="p">,</span><span class="n">lsa</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa1</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">pmem1</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">downstream</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">2</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">us0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">swport2</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">6</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">swport2</span><span class="p">,</span><span class="n">persistent</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem2</span><span class="p">,</span><span class="n">lsa</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa2</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">pmem2</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">downstream</span><span class="p">,</span><span class="n">port</span><span class="o">=</span><span class="mi">3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">us0</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">swport3</span><span class="p">,</span><span class="n">chassis</span><span class="o">=</span><span class="mi">0</span><span class="p">,</span><span class="n">slot</span><span class="o">=</span><span class="mi">7</span> \
|
||
<span class="o">-</span><span class="n">device</span> <span class="n">cxl</span><span class="o">-</span><span class="n">type3</span><span class="p">,</span><span class="n">bus</span><span class="o">=</span><span class="n">swport3</span><span class="p">,</span><span class="n">persistent</span><span class="o">-</span><span class="n">memdev</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">mem3</span><span class="p">,</span><span class="n">lsa</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">lsa3</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">cxl</span><span class="o">-</span><span class="n">pmem3</span> \
|
||
<span class="o">-</span><span class="n">M</span> <span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">targets</span><span class="mf">.0</span><span class="o">=</span><span class="n">cxl</span><span class="mf">.1</span><span class="p">,</span><span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">size</span><span class="o">=</span><span class="mi">4</span><span class="n">G</span><span class="p">,</span><span class="n">cxl</span><span class="o">-</span><span class="n">fmw</span><span class="mf">.0</span><span class="o">.</span><span class="n">interleave</span><span class="o">-</span><span class="n">granularity</span><span class="o">=</span><span class="mi">4</span><span class="n">k</span>
|
||
</pre></div>
|
||
</div>
|
||
</section>
|
||
<section id="deprecations">
|
||
<h2>Deprecations<a class="headerlink" href="#deprecations" title="Link to this heading"></a></h2>
|
||
<p>The Type 3 device [memdev] attribute has been deprecated in favor of the
|
||
[persistent-memdev] attributes. [memdev] will default to a persistent memory
|
||
device for backward compatibility and is incapable of being used in combination
|
||
with [persistent-memdev].</p>
|
||
</section>
|
||
<section id="kernel-configuration-options">
|
||
<h2>Kernel Configuration Options<a class="headerlink" href="#kernel-configuration-options" title="Link to this heading"></a></h2>
|
||
<p>In Linux 5.18 the following options are necessary to make use of
|
||
OS management of CXL memory devices as described here.</p>
|
||
<ul class="simple">
|
||
<li><p>CONFIG_CXL_BUS</p></li>
|
||
<li><p>CONFIG_CXL_PCI</p></li>
|
||
<li><p>CONFIG_CXL_ACPI</p></li>
|
||
<li><p>CONFIG_CXL_PMEM</p></li>
|
||
<li><p>CONFIG_CXL_MEM</p></li>
|
||
<li><p>CONFIG_CXL_PORT</p></li>
|
||
<li><p>CONFIG_CXL_REGION</p></li>
|
||
</ul>
|
||
</section>
|
||
<section id="references">
|
||
<h2>References<a class="headerlink" href="#references" title="Link to this heading"></a></h2>
|
||
<blockquote>
|
||
<div><ul class="simple">
|
||
<li><p>Consortium website for specifications etc:
|
||
<a class="reference external" href="http://www.computeexpresslink.org">http://www.computeexpresslink.org</a></p></li>
|
||
<li><p>Compute Express link Revision 2 specification, October 2020</p></li>
|
||
<li><p>CEDT CFMWS & QTG _DSM ECN May 2021</p></li>
|
||
</ul>
|
||
</div></blockquote>
|
||
</section>
|
||
</section>
|
||
|
||
|
||
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|
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||
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||
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||
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||
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<p>This documentation is for QEMU version 8.2.2.</p>
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||
<p><a href="../../about/license.html">QEMU and this manual are released under the
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