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<section id="software-guard-extensions-sgx">
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<h1>Software Guard eXtensions (SGX)<a class="headerlink" href="#software-guard-extensions-sgx" title="Link to this heading"></a></h1>
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<section id="overview">
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<h2>Overview<a class="headerlink" href="#overview" title="Link to this heading"></a></h2>
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<p>Intel Software Guard eXtensions (SGX) is a set of instructions and mechanisms
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for memory accesses in order to provide security accesses for sensitive
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applications and data. SGX allows an application to use it’s pariticular
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address space as an <em>enclave</em>, which is a protected area provides confidentiality
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and integrity even in the presence of privileged malware. Accesses to the
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enclave memory area from any software not resident in the enclave are prevented,
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including those from privileged software.</p>
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</section>
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<section id="virtual-sgx">
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<h2>Virtual SGX<a class="headerlink" href="#virtual-sgx" title="Link to this heading"></a></h2>
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<p>SGX feature is exposed to guest via SGX CPUID. Looking at SGX CPUID, we can
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report the same CPUID info to guest as on host for most of SGX CPUID. With
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reporting the same CPUID guest is able to use full capacity of SGX, and KVM
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doesn’t need to emulate those info.</p>
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<p>The guest’s EPC base and size are determined by QEMU, and KVM needs QEMU to
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notify such info to it before it can initialize SGX for guest.</p>
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<section id="virtual-epc">
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<h3>Virtual EPC<a class="headerlink" href="#virtual-epc" title="Link to this heading"></a></h3>
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<p>By default, QEMU does not assign EPC to a VM, i.e. fully enabling SGX in a VM
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requires explicit allocation of EPC to the VM. Similar to other specialized
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memory types, e.g. hugetlbfs, EPC is exposed as a memory backend.</p>
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<p>SGX EPC is enumerated through CPUID, i.e. EPC “devices” need to be realized
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prior to realizing the vCPUs themselves, which occurs long before generic
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devices are parsed and realized. This limitation means that EPC does not
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require -maxmem as EPC is not treated as {cold,hot}plugged memory.</p>
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<p>QEMU does not artificially restrict the number of EPC sections exposed to a
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guest, e.g. QEMU will happily allow you to create 64 1M EPC sections. Be aware
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that some kernels may not recognize all EPC sections, e.g. the Linux SGX driver
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is hardwired to support only 8 EPC sections.</p>
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<p>The following QEMU snippet creates two EPC sections, with 64M pre-allocated
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to the VM and an additional 28M mapped but not allocated:</p>
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<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">epc</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">mem1</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">64</span><span class="n">M</span><span class="p">,</span><span class="n">prealloc</span><span class="o">=</span><span class="n">on</span> \
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<span class="o">-</span><span class="nb">object</span> <span class="n">memory</span><span class="o">-</span><span class="n">backend</span><span class="o">-</span><span class="n">epc</span><span class="p">,</span><span class="nb">id</span><span class="o">=</span><span class="n">mem2</span><span class="p">,</span><span class="n">size</span><span class="o">=</span><span class="mi">28</span><span class="n">M</span> \
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<span class="o">-</span><span class="n">M</span> <span class="n">sgx</span><span class="o">-</span><span class="n">epc</span><span class="mf">.0</span><span class="o">.</span><span class="n">memdev</span><span class="o">=</span><span class="n">mem1</span><span class="p">,</span><span class="n">sgx</span><span class="o">-</span><span class="n">epc</span><span class="mf">.1</span><span class="o">.</span><span class="n">memdev</span><span class="o">=</span><span class="n">mem2</span>
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</pre></div>
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</div>
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<p>Note:</p>
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<p>The size and location of the virtual EPC are far less restricted compared
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to physical EPC. Because physical EPC is protected via range registers,
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the size of the physical EPC must be a power of two (though software sees
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a subset of the full EPC, e.g. 92M or 128M) and the EPC must be naturally
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aligned. KVM SGX’s virtual EPC is purely a software construct and only
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requires the size and location to be page aligned. QEMU enforces the EPC
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size is a multiple of 4k and will ensure the base of the EPC is 4k aligned.
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To simplify the implementation, EPC is always located above 4g in the guest
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physical address space.</p>
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</section>
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<section id="migration">
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<h3>Migration<a class="headerlink" href="#migration" title="Link to this heading"></a></h3>
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<p>QEMU/KVM doesn’t prevent live migrating SGX VMs, although from hardware’s
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perspective, SGX doesn’t support live migration, since both EPC and the SGX
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key hierarchy are bound to the physical platform. However live migration
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can be supported in the sense if guest software stack can support recreating
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enclaves when it suffers sudden lose of EPC; and if guest enclaves can detect
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SGX keys being changed, and handle gracefully. For instance, when ERESUME fails
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with #PF.SGX, guest software can gracefully detect it and recreate enclaves;
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and when enclave fails to unseal sensitive information from outside, it can
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detect such error and sensitive information can be provisioned to it again.</p>
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</section>
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<section id="cpuid">
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<h3>CPUID<a class="headerlink" href="#cpuid" title="Link to this heading"></a></h3>
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<p>Due to its myriad dependencies, SGX is currently not listed as supported
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in any of QEMU’s built-in CPU configuration. To expose SGX (and SGX Launch
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Control) to a guest, you must either use <code class="docutils literal notranslate"><span class="pre">-cpu</span> <span class="pre">host</span></code> to pass-through the
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host CPU model, or explicitly enable SGX when using a built-in CPU model,
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e.g. via <code class="docutils literal notranslate"><span class="pre">-cpu</span> <span class="pre"><model>,+sgx</span></code> or <code class="docutils literal notranslate"><span class="pre">-cpu</span> <span class="pre"><model>,+sgx,+sgxlc</span></code>.</p>
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<p>All SGX sub-features enumerated through CPUID, e.g. SGX2, MISCSELECT,
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ATTRIBUTES, etc… can be restricted via CPUID flags. Be aware that enforcing
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restriction of MISCSELECT, ATTRIBUTES and XFRM requires intercepting ECREATE,
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i.e. may marginally reduce SGX performance in the guest. All SGX sub-features
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controlled via -cpu are prefixed with “sgx”, e.g.:</p>
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||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>$ qemu-system-x86_64 -cpu help | xargs printf "%s\n" | grep sgx
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sgx
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sgx-debug
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sgx-encls-c
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sgx-enclv
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sgx-exinfo
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sgx-kss
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sgx-mode64
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sgx-provisionkey
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sgx-tokenkey
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sgx1
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sgx2
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sgxlc
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</pre></div>
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</div>
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<p>The following QEMU snippet passes through the host CPU but restricts access to
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the provision and EINIT token keys:</p>
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<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o">-</span><span class="n">cpu</span> <span class="n">host</span><span class="p">,</span><span class="o">-</span><span class="n">sgx</span><span class="o">-</span><span class="n">provisionkey</span><span class="p">,</span><span class="o">-</span><span class="n">sgx</span><span class="o">-</span><span class="n">tokenkey</span>
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</pre></div>
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</div>
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<p>SGX sub-features cannot be emulated, i.e. sub-features that are not present
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in hardware cannot be forced on via ‘-cpu’.</p>
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</section>
|
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<section id="virtualize-sgx-launch-control">
|
||
<h3>Virtualize SGX Launch Control<a class="headerlink" href="#virtualize-sgx-launch-control" title="Link to this heading"></a></h3>
|
||
<p>QEMU SGX support for Launch Control (LC) is passive, in the sense that it
|
||
does not actively change the LC configuration. QEMU SGX provides the user
|
||
the ability to set/clear the CPUID flag (and by extension the associated
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||
IA32_FEATURE_CONTROL MSR bit in fw_cfg) and saves/restores the LE Hash MSRs
|
||
when getting/putting guest state, but QEMU does not add new controls to
|
||
directly modify the LC configuration. Similar to hardware behavior, locking
|
||
the LC configuration to a non-Intel value is left to guest firmware. Unlike
|
||
host bios setting for SGX launch control(LC), there is no special bios setting
|
||
for SGX guest by our design. If host is in locked mode, we can still allow
|
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creating VM with SGX.</p>
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||
</section>
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||
<section id="feature-control">
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<h3>Feature Control<a class="headerlink" href="#feature-control" title="Link to this heading"></a></h3>
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<p>QEMU SGX updates the <code class="docutils literal notranslate"><span class="pre">etc/msr_feature_control</span></code> fw_cfg entry to set the SGX
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(bit 18) and SGX LC (bit 17) flags based on their respective CPUID support,
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i.e. existing guest firmware will automatically set SGX and SGX LC accordingly,
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assuming said firmware supports fw_cfg.msr_feature_control.</p>
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</section>
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||
</section>
|
||
<section id="launching-a-guest">
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<h2>Launching a guest<a class="headerlink" href="#launching-a-guest" title="Link to this heading"></a></h2>
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<p>To launch a SGX guest:</p>
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<pre class="literal-block">qemu-system-x86_64 \
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-cpu host,+sgx-provisionkey \
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-object memory-backend-epc,id=mem1,size=64M,prealloc=on \
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-M sgx-epc.0.memdev=mem1,sgx-epc.0.node=0</pre>
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<p>Utilizing SGX in the guest requires a kernel/OS with SGX support.
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The support can be determined in guest by:</p>
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<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>$ grep sgx /proc/cpuinfo
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</pre></div>
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</div>
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<p>and SGX epc info by:</p>
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<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>$ dmesg | grep sgx
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[ 0.182807] sgx: EPC section 0x140000000-0x143ffffff
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[ 0.183695] sgx: [Firmware Bug]: Unable to map EPC section to online node. Fallback to the NUMA node 0.
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</pre></div>
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</div>
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<p>To launch a SGX numa guest:</p>
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<pre class="literal-block">qemu-system-x86_64 \
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-cpu host,+sgx-provisionkey \
|
||
-object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \
|
||
-object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \
|
||
-numa node,nodeid=0,cpus=0-1,memdev=node0 \
|
||
-object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \
|
||
-object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
|
||
-numa node,nodeid=1,cpus=2-3,memdev=node1 \
|
||
-M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1</pre>
|
||
<p>and SGX epc numa info by:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span>$ dmesg | grep sgx
|
||
[ 0.369937] sgx: EPC section 0x180000000-0x183ffffff
|
||
[ 0.370259] sgx: EPC section 0x184000000-0x185bfffff
|
||
|
||
$ dmesg | grep SRAT
|
||
[ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
|
||
[ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
|
||
</pre></div>
|
||
</div>
|
||
</section>
|
||
<section id="references">
|
||
<h2>References<a class="headerlink" href="#references" title="Link to this heading"></a></h2>
|
||
<ul class="simple">
|
||
<li><p><a class="reference external" href="https://software.intel.com/sgx">SGX Homepage</a></p></li>
|
||
<li><p><a class="reference external" href="https://github.com/intel/linux-sgx.git">SGX SDK</a></p></li>
|
||
<li><p>SGX specification: Intel SDM Volume 3</p></li>
|
||
</ul>
|
||
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