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<section id="openrisc-1000-cpu-architecture-support">
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<h1>OpenRISC 1000 CPU architecture support<a class="headerlink" href="#openrisc-1000-cpu-architecture-support" title="Link to this heading"></a></h1>
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<p>QEMU’s TCG emulation includes support for the OpenRISC or1200 implementation of
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the OpenRISC 1000 cpu architecture.</p>
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<p>The or1200 cpu also has support for the following instruction subsets:</p>
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<ul class="simple">
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<li><p>ORBIS32 (OpenRISC Basic Instruction Set)</p></li>
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<li><p>ORFPX32 (OpenRISC Floating-Point eXtension)</p></li>
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</ul>
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<p>In addition to the instruction subsets the QEMU TCG emulation also has support
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for most Class II (optional) instructions.</p>
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<p>For information on all OpenRISC instructions please refer to the latest
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architecture manual available on the OpenRISC website in the
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<a class="reference external" href="https://openrisc.io/architecture">OpenRISC Architecture</a> section.</p>
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