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<a href="https://gitlab.com/qemu-project/qemu/blob/master/docs/system/qemu-cpu-models.rst" class="fa fa-gitlab"> Edit on GitLab</a>
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<section id="qemu-kvm-cpu-model-configuration">
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<h1>QEMU / KVM CPU model configuration<a class="headerlink" href="#qemu-kvm-cpu-model-configuration" title="Link to this heading"></a></h1>
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<section id="synopsis">
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<h2>Synopsis<a class="headerlink" href="#synopsis" title="Link to this heading"></a></h2>
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<p>QEMU CPU Modelling Infrastructure manual</p>
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</section>
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<section id="description">
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<h2>Description<a class="headerlink" href="#description" title="Link to this heading"></a></h2>
|
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<section id="recommendations-for-kvm-cpu-model-configuration-on-x86-hosts">
|
||
<h3>Recommendations for KVM CPU model configuration on x86 hosts<a class="headerlink" href="#recommendations-for-kvm-cpu-model-configuration-on-x86-hosts" title="Link to this heading"></a></h3>
|
||
<p>The information that follows provides recommendations for configuring
|
||
CPU models on x86 hosts. The goals are to maximise performance, while
|
||
protecting guest OS against various CPU hardware flaws, and optionally
|
||
enabling live migration between hosts with heterogeneous CPU models.</p>
|
||
<section id="two-ways-to-configure-cpu-models-with-qemu-kvm">
|
||
<h4>Two ways to configure CPU models with QEMU / KVM<a class="headerlink" href="#two-ways-to-configure-cpu-models-with-qemu-kvm" title="Link to this heading"></a></h4>
|
||
<ol class="arabic">
|
||
<li><p><strong>Host passthrough</strong></p>
|
||
<p>This passes the host CPU model features, model, stepping, exactly to
|
||
the guest. Note that KVM may filter out some host CPU model features
|
||
if they cannot be supported with virtualization. Live migration is
|
||
unsafe when this mode is used as libvirt / QEMU cannot guarantee a
|
||
stable CPU is exposed to the guest across hosts. This is the
|
||
recommended CPU to use, provided live migration is not required.</p>
|
||
</li>
|
||
<li><p><strong>Named model</strong></p>
|
||
<p>QEMU comes with a number of predefined named CPU models, that
|
||
typically refer to specific generations of hardware released by
|
||
Intel and AMD. These allow the guest VMs to have a degree of
|
||
isolation from the host CPU, allowing greater flexibility in live
|
||
migrating between hosts with differing hardware. @end table</p>
|
||
</li>
|
||
</ol>
|
||
<p>In both cases, it is possible to optionally add or remove individual CPU
|
||
features, to alter what is presented to the guest by default.</p>
|
||
<p>Libvirt supports a third way to configure CPU models known as “Host
|
||
model”. This uses the QEMU “Named model” feature, automatically picking
|
||
a CPU model that is similar the host CPU, and then adding extra features
|
||
to approximate the host model as closely as possible. This does not
|
||
guarantee the CPU family, stepping, etc will precisely match the host
|
||
CPU, as they would with “Host passthrough”, but gives much of the
|
||
benefit of passthrough, while making live migration safe.</p>
|
||
</section>
|
||
<section id="abi-compatibility-levels-for-cpu-models">
|
||
<h4>ABI compatibility levels for CPU models<a class="headerlink" href="#abi-compatibility-levels-for-cpu-models" title="Link to this heading"></a></h4>
|
||
<p>The x86_64 architecture has a number of <a class="reference external" href="https://gitlab.com/x86-psABIs/x86-64-ABI/">ABI compatibility levels</a>
|
||
defined. Traditionally most operating systems and toolchains would
|
||
only target the original baseline ABI. It is expected that in
|
||
future OS and toolchains are likely to target newer ABIs. The
|
||
table that follows illustrates which ABI compatibility levels
|
||
can be satisfied by the QEMU CPU models. Note that the table only
|
||
lists the long term stable CPU model versions (eg Haswell-v4).
|
||
In addition to what is listed, there are also many CPU model
|
||
aliases which resolve to a different CPU model version,
|
||
depending on the machine type is in use.</p>
|
||
<table class="docutils align-default" id="id1">
|
||
<caption><span class="caption-text">x86-64 ABI compatibility levels</span><a class="headerlink" href="#id1" title="Link to this table"></a></caption>
|
||
<colgroup>
|
||
<col style="width: 40.0%" />
|
||
<col style="width: 15.0%" />
|
||
<col style="width: 15.0%" />
|
||
<col style="width: 15.0%" />
|
||
<col style="width: 15.0%" />
|
||
</colgroup>
|
||
<thead>
|
||
<tr class="row-odd"><th class="head"><p>Model</p></th>
|
||
<th class="head"><p>baseline</p></th>
|
||
<th class="head"><p>v2</p></th>
|
||
<th class="head"><p>v3</p></th>
|
||
<th class="head"><p>v4</p></th>
|
||
</tr>
|
||
<tr class="row-even"><th class="head"><p>486-v1</p></th>
|
||
<th class="head"></th>
|
||
<th class="head"></th>
|
||
<th class="head"></th>
|
||
<th class="head"></th>
|
||
</tr>
|
||
</thead>
|
||
<tbody>
|
||
<tr class="row-odd"><td><p>Broadwell-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Broadwell-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Broadwell-v3</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Broadwell-v4</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Cascadelake-Server-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Cascadelake-Server-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Cascadelake-Server-v3</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Cascadelake-Server-v4</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Conroe-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Cooperlake-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Denverton-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Denverton-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Dhyana-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>EPYC-Milan-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>EPYC-Rome-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>EPYC-Rome-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>EPYC-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>EPYC-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>EPYC-v3</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Haswell-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Haswell-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Haswell-v3</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Haswell-v4</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Icelake-Client-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Icelake-Client-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Icelake-Server-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Icelake-Server-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Icelake-Server-v3</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Icelake-Server-v4</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>IvyBridge-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>IvyBridge-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>KnightsMill-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Nehalem-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Nehalem-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Opteron_G1-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Opteron_G2-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Opteron_G3-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Opteron_G4-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Opteron_G5-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Penryn-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>SandyBridge-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>SandyBridge-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Skylake-Client-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Skylake-Client-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Skylake-Client-v3</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Skylake-Server-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Skylake-Server-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Skylake-Server-v3</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Skylake-Server-v4</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Snowridge-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Snowridge-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>Westmere-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>Westmere-v2</p></td>
|
||
<td><p>✅</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>athlon-v1</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>core2duo-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>coreduo-v1</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>kvm32-v1</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>kvm64-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>n270-v1</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>pentium-v1</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>pentium2-v1</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>pentium3-v1</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>phenom-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-even"><td><p>qemu32-v1</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
<tr class="row-odd"><td><p>qemu64-v1</p></td>
|
||
<td><p>✅</p></td>
|
||
<td></td>
|
||
<td></td>
|
||
<td></td>
|
||
</tr>
|
||
</tbody>
|
||
</table>
|
||
</section>
|
||
<section id="preferred-cpu-models-for-intel-x86-hosts">
|
||
<h4>Preferred CPU models for Intel x86 hosts<a class="headerlink" href="#preferred-cpu-models-for-intel-x86-hosts" title="Link to this heading"></a></h4>
|
||
<p>The following CPU models are preferred for use on Intel hosts.
|
||
Administrators / applications are recommended to use the CPU model that
|
||
matches the generation of the host CPUs in use. In a deployment with a
|
||
mixture of host CPU models between machines, if live migration
|
||
compatibility is required, use the newest CPU model that is compatible
|
||
across all desired hosts.</p>
|
||
<dl class="simple">
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Cascadelake-Server</span></code>, <code class="docutils literal notranslate"><span class="pre">Cascadelake-Server-noTSX</span></code></dt><dd><p>Intel Xeon Processor (Cascade Lake, 2019), with “stepping” levels 6
|
||
or 7 only. (The Cascade Lake Xeon processor with <em>stepping 5 is
|
||
vulnerable to MDS variants</em>.)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Skylake-Server</span></code>, <code class="docutils literal notranslate"><span class="pre">Skylake-Server-IBRS</span></code>, <code class="docutils literal notranslate"><span class="pre">Skylake-Server-IBRS-noTSX</span></code></dt><dd><p>Intel Xeon Processor (Skylake, 2016)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Skylake-Client</span></code>, <code class="docutils literal notranslate"><span class="pre">Skylake-Client-IBRS</span></code>, <code class="docutils literal notranslate"><span class="pre">Skylake-Client-noTSX-IBRS}</span></code></dt><dd><p>Intel Core Processor (Skylake, 2015)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Broadwell</span></code>, <code class="docutils literal notranslate"><span class="pre">Broadwell-IBRS</span></code>, <code class="docutils literal notranslate"><span class="pre">Broadwell-noTSX</span></code>, <code class="docutils literal notranslate"><span class="pre">Broadwell-noTSX-IBRS</span></code></dt><dd><p>Intel Core Processor (Broadwell, 2014)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Haswell</span></code>, <code class="docutils literal notranslate"><span class="pre">Haswell-IBRS</span></code>, <code class="docutils literal notranslate"><span class="pre">Haswell-noTSX</span></code>, <code class="docutils literal notranslate"><span class="pre">Haswell-noTSX-IBRS</span></code></dt><dd><p>Intel Core Processor (Haswell, 2013)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">IvyBridge</span></code>, <code class="docutils literal notranslate"><span class="pre">IvyBridge-IBR</span></code></dt><dd><p>Intel Xeon E3-12xx v2 (Ivy Bridge, 2012)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">SandyBridge</span></code>, <code class="docutils literal notranslate"><span class="pre">SandyBridge-IBRS</span></code></dt><dd><p>Intel Xeon E312xx (Sandy Bridge, 2011)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Westmere</span></code>, <code class="docutils literal notranslate"><span class="pre">Westmere-IBRS</span></code></dt><dd><p>Westmere E56xx/L56xx/X56xx (Nehalem-C, 2010)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Nehalem</span></code>, <code class="docutils literal notranslate"><span class="pre">Nehalem-IBRS</span></code></dt><dd><p>Intel Core i7 9xx (Nehalem Class Core i7, 2008)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Penryn</span></code></dt><dd><p>Intel Core 2 Duo P9xxx (Penryn Class Core 2, 2007)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Conroe</span></code></dt><dd><p>Intel Celeron_4x0 (Conroe/Merom Class Core 2, 2006)</p>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
<section id="important-cpu-features-for-intel-x86-hosts">
|
||
<h4>Important CPU features for Intel x86 hosts<a class="headerlink" href="#important-cpu-features-for-intel-x86-hosts" title="Link to this heading"></a></h4>
|
||
<p>The following are important CPU features that should be used on Intel
|
||
x86 hosts, when available in the host CPU. Some of them require explicit
|
||
configuration to enable, as they are not included by default in some, or
|
||
all, of the named CPU models listed above. In general all of these
|
||
features are included if using “Host passthrough” or “Host model”.</p>
|
||
<dl>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">pcid</span></code></dt><dd><p>Recommended to mitigate the cost of the Meltdown (CVE-2017-5754) fix.</p>
|
||
<p>Included by default in Haswell, Broadwell & Skylake Intel CPU models.</p>
|
||
<p>Should be explicitly turned on for Westmere, SandyBridge, and
|
||
IvyBridge Intel CPU models. Note that some desktop/mobile Westmere
|
||
CPUs cannot support this feature.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">spec-ctrl</span></code></dt><dd><p>Required to enable the Spectre v2 (CVE-2017-5715) fix.</p>
|
||
<p>Included by default in Intel CPU models with -IBRS suffix.</p>
|
||
<p>Must be explicitly turned on for Intel CPU models without -IBRS
|
||
suffix.</p>
|
||
<p>Requires the host CPU microcode to support this feature before it
|
||
can be used for guest CPUs.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">stibp</span></code></dt><dd><p>Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some
|
||
operating systems.</p>
|
||
<p>Must be explicitly turned on for all Intel CPU models.</p>
|
||
<p>Requires the host CPU microcode to support this feature before it can
|
||
be used for guest CPUs.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">ssbd</span></code></dt><dd><p>Required to enable the CVE-2018-3639 fix.</p>
|
||
<p>Not included by default in any Intel CPU model.</p>
|
||
<p>Must be explicitly turned on for all Intel CPU models.</p>
|
||
<p>Requires the host CPU microcode to support this feature before it
|
||
can be used for guest CPUs.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">pdpe1gb</span></code></dt><dd><p>Recommended to allow guest OS to use 1GB size pages.</p>
|
||
<p>Not included by default in any Intel CPU model.</p>
|
||
<p>Should be explicitly turned on for all Intel CPU models.</p>
|
||
<p>Note that not all CPU hardware will support this feature.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">md-clear</span></code></dt><dd><p>Required to confirm the MDS (CVE-2018-12126, CVE-2018-12127,
|
||
CVE-2018-12130, CVE-2019-11091) fixes.</p>
|
||
<p>Not included by default in any Intel CPU model.</p>
|
||
<p>Must be explicitly turned on for all Intel CPU models.</p>
|
||
<p>Requires the host CPU microcode to support this feature before it
|
||
can be used for guest CPUs.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">mds-no</span></code></dt><dd><p>Recommended to inform the guest OS that the host is <em>not</em> vulnerable
|
||
to any of the MDS variants ([MFBDS] CVE-2018-12130, [MLPDS]
|
||
CVE-2018-12127, [MSBDS] CVE-2018-12126).</p>
|
||
<p>This is an MSR (Model-Specific Register) feature rather than a CPUID feature,
|
||
so it will not appear in the Linux <code class="docutils literal notranslate"><span class="pre">/proc/cpuinfo</span></code> in the host or
|
||
guest. Instead, the host kernel uses it to populate the MDS
|
||
vulnerability file in <code class="docutils literal notranslate"><span class="pre">sysfs</span></code>.</p>
|
||
<p>So it should only be enabled for VMs if the host reports @code{Not
|
||
affected} in the <code class="docutils literal notranslate"><span class="pre">/sys/devices/system/cpu/vulnerabilities/mds</span></code> file.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">taa-no</span></code></dt><dd><p>Recommended to inform that the guest that the host is <code class="docutils literal notranslate"><span class="pre">not</span></code>
|
||
vulnerable to CVE-2019-11135, TSX Asynchronous Abort (TAA).</p>
|
||
<p>This too is an MSR feature, so it does not show up in the Linux
|
||
<code class="docutils literal notranslate"><span class="pre">/proc/cpuinfo</span></code> in the host or guest.</p>
|
||
<p>It should only be enabled for VMs if the host reports <code class="docutils literal notranslate"><span class="pre">Not</span> <span class="pre">affected</span></code>
|
||
in the <code class="docutils literal notranslate"><span class="pre">/sys/devices/system/cpu/vulnerabilities/tsx_async_abort</span></code>
|
||
file.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">tsx-ctrl</span></code></dt><dd><p>Recommended to inform the guest that it can disable the Intel TSX
|
||
(Transactional Synchronization Extensions) feature; or, if the
|
||
processor is vulnerable, use the Intel VERW instruction (a
|
||
processor-level instruction that performs checks on memory access) as
|
||
a mitigation for the TAA vulnerability. (For details, refer to
|
||
Intel’s <a class="reference external" href="https://software.intel.com/security-software-guidance/insights/deep-dive-intel-analysis-microarchitectural-data-sampling">deep dive into MDS</a>.)</p>
|
||
<p>Expose this to the guest OS if and only if: (a) the host has TSX
|
||
enabled; <em>and</em> (b) the guest has <code class="docutils literal notranslate"><span class="pre">rtm</span></code> CPU flag enabled.</p>
|
||
<p>By disabling TSX, KVM-based guests can avoid paying the price of
|
||
mitigating TSX-based attacks.</p>
|
||
<p>Note that <code class="docutils literal notranslate"><span class="pre">tsx-ctrl</span></code> too is an MSR feature, so it does not show
|
||
up in the Linux <code class="docutils literal notranslate"><span class="pre">/proc/cpuinfo</span></code> in the host or guest.</p>
|
||
<p>To validate that Intel TSX is indeed disabled for the guest, there are
|
||
two ways: (a) check for the <em>absence</em> of <code class="docutils literal notranslate"><span class="pre">rtm</span></code> in the guest’s
|
||
<code class="docutils literal notranslate"><span class="pre">/proc/cpuinfo</span></code>; or (b) the
|
||
<code class="docutils literal notranslate"><span class="pre">/sys/devices/system/cpu/vulnerabilities/tsx_async_abort</span></code> file in
|
||
the guest should report <code class="docutils literal notranslate"><span class="pre">Mitigation:</span> <span class="pre">TSX</span> <span class="pre">disabled</span></code>.</p>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
<section id="preferred-cpu-models-for-amd-x86-hosts">
|
||
<h4>Preferred CPU models for AMD x86 hosts<a class="headerlink" href="#preferred-cpu-models-for-amd-x86-hosts" title="Link to this heading"></a></h4>
|
||
<p>The following CPU models are preferred for use on AMD hosts.
|
||
Administrators / applications are recommended to use the CPU model that
|
||
matches the generation of the host CPUs in use. In a deployment with a
|
||
mixture of host CPU models between machines, if live migration
|
||
compatibility is required, use the newest CPU model that is compatible
|
||
across all desired hosts.</p>
|
||
<dl class="simple">
|
||
<dt><code class="docutils literal notranslate"><span class="pre">EPYC</span></code>, <code class="docutils literal notranslate"><span class="pre">EPYC-IBPB</span></code></dt><dd><p>AMD EPYC Processor (2017)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Opteron_G5</span></code></dt><dd><p>AMD Opteron 63xx class CPU (2012)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Opteron_G4</span></code></dt><dd><p>AMD Opteron 62xx class CPU (2011)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Opteron_G3</span></code></dt><dd><p>AMD Opteron 23xx (Gen 3 Class Opteron, 2009)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Opteron_G2</span></code></dt><dd><p>AMD Opteron 22xx (Gen 2 Class Opteron, 2006)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Opteron_G1</span></code></dt><dd><p>AMD Opteron 240 (Gen 1 Class Opteron, 2004)</p>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
<section id="important-cpu-features-for-amd-x86-hosts">
|
||
<h4>Important CPU features for AMD x86 hosts<a class="headerlink" href="#important-cpu-features-for-amd-x86-hosts" title="Link to this heading"></a></h4>
|
||
<p>The following are important CPU features that should be used on AMD x86
|
||
hosts, when available in the host CPU. Some of them require explicit
|
||
configuration to enable, as they are not included by default in some, or
|
||
all, of the named CPU models listed above. In general all of these
|
||
features are included if using “Host passthrough” or “Host model”.</p>
|
||
<dl>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">ibpb</span></code></dt><dd><p>Required to enable the Spectre v2 (CVE-2017-5715) fix.</p>
|
||
<p>Included by default in AMD CPU models with -IBPB suffix.</p>
|
||
<p>Must be explicitly turned on for AMD CPU models without -IBPB suffix.</p>
|
||
<p>Requires the host CPU microcode to support this feature before it
|
||
can be used for guest CPUs.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">stibp</span></code></dt><dd><p>Required to enable stronger Spectre v2 (CVE-2017-5715) fixes in some
|
||
operating systems.</p>
|
||
<p>Must be explicitly turned on for all AMD CPU models.</p>
|
||
<p>Requires the host CPU microcode to support this feature before it
|
||
can be used for guest CPUs.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">virt-ssbd</span></code></dt><dd><p>Required to enable the CVE-2018-3639 fix</p>
|
||
<p>Not included by default in any AMD CPU model.</p>
|
||
<p>Must be explicitly turned on for all AMD CPU models.</p>
|
||
<p>This should be provided to guests, even if amd-ssbd is also provided,
|
||
for maximum guest compatibility.</p>
|
||
<p>Note for some QEMU / libvirt versions, this must be force enabled when
|
||
when using “Host model”, because this is a virtual feature that
|
||
doesn’t exist in the physical host CPUs.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">amd-ssbd</span></code></dt><dd><p>Required to enable the CVE-2018-3639 fix</p>
|
||
<p>Not included by default in any AMD CPU model.</p>
|
||
<p>Must be explicitly turned on for all AMD CPU models.</p>
|
||
<p>This provides higher performance than <code class="docutils literal notranslate"><span class="pre">virt-ssbd</span></code> so should be
|
||
exposed to guests whenever available in the host. <code class="docutils literal notranslate"><span class="pre">virt-ssbd</span></code> should
|
||
none the less also be exposed for maximum guest compatibility as some
|
||
kernels only know about <code class="docutils literal notranslate"><span class="pre">virt-ssbd</span></code>.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">amd-no-ssb</span></code></dt><dd><p>Recommended to indicate the host is not vulnerable CVE-2018-3639</p>
|
||
<p>Not included by default in any AMD CPU model.</p>
|
||
<p>Future hardware generations of CPU will not be vulnerable to
|
||
CVE-2018-3639, and thus the guest should be told not to enable
|
||
its mitigations, by exposing amd-no-ssb. This is mutually
|
||
exclusive with virt-ssbd and amd-ssbd.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">pdpe1gb</span></code></dt><dd><p>Recommended to allow guest OS to use 1GB size pages</p>
|
||
<p>Not included by default in any AMD CPU model.</p>
|
||
<p>Should be explicitly turned on for all AMD CPU models.</p>
|
||
<p>Note that not all CPU hardware will support this feature.</p>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
<section id="default-x86-cpu-models">
|
||
<h4>Default x86 CPU models<a class="headerlink" href="#default-x86-cpu-models" title="Link to this heading"></a></h4>
|
||
<p>The default QEMU CPU models are designed such that they can run on all
|
||
hosts. If an application does not wish to do perform any host
|
||
compatibility checks before launching guests, the default is guaranteed
|
||
to work.</p>
|
||
<p>The default CPU models will, however, leave the guest OS vulnerable to
|
||
various CPU hardware flaws, so their use is strongly discouraged.
|
||
Applications should follow the earlier guidance to setup a better CPU
|
||
configuration, with host passthrough recommended if live migration is
|
||
not needed.</p>
|
||
<dl class="simple">
|
||
<dt><code class="docutils literal notranslate"><span class="pre">qemu32</span></code>, <code class="docutils literal notranslate"><span class="pre">qemu64</span></code></dt><dd><p>QEMU Virtual CPU version 2.5+ (32 & 64 bit variants)</p>
|
||
</dd>
|
||
</dl>
|
||
<p><code class="docutils literal notranslate"><span class="pre">qemu64</span></code> is used for x86_64 guests and <code class="docutils literal notranslate"><span class="pre">qemu32</span></code> is used for i686
|
||
guests, when no <code class="docutils literal notranslate"><span class="pre">-cpu</span></code> argument is given to QEMU, or no <code class="docutils literal notranslate"><span class="pre"><cpu></span></code> is
|
||
provided in libvirt XML.</p>
|
||
</section>
|
||
<section id="other-non-recommended-x86-cpus">
|
||
<h4>Other non-recommended x86 CPUs<a class="headerlink" href="#other-non-recommended-x86-cpus" title="Link to this heading"></a></h4>
|
||
<p>The following CPUs models are compatible with most AMD and Intel x86
|
||
hosts, but their usage is discouraged, as they expose a very limited
|
||
featureset, which prevents guests having optimal performance.</p>
|
||
<dl>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">kvm32</span></code>, <code class="docutils literal notranslate"><span class="pre">kvm64</span></code></dt><dd><p>Common KVM processor (32 & 64 bit variants).</p>
|
||
<p>Legacy models just for historical compatibility with ancient QEMU
|
||
versions.</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">486</span></code>, <code class="docutils literal notranslate"><span class="pre">athlon</span></code>, <code class="docutils literal notranslate"><span class="pre">phenom</span></code>, <code class="docutils literal notranslate"><span class="pre">coreduo</span></code>, <code class="docutils literal notranslate"><span class="pre">core2duo</span></code>, <code class="docutils literal notranslate"><span class="pre">n270</span></code>, <code class="docutils literal notranslate"><span class="pre">pentium</span></code>, <code class="docutils literal notranslate"><span class="pre">pentium2</span></code>, <code class="docutils literal notranslate"><span class="pre">pentium3</span></code></dt><dd><p>Various very old x86 CPU models, mostly predating the introduction
|
||
of hardware assisted virtualization, that should thus not be
|
||
required for running virtual machines.</p>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
</section>
|
||
<section id="syntax-for-configuring-cpu-models">
|
||
<h3>Syntax for configuring CPU models<a class="headerlink" href="#syntax-for-configuring-cpu-models" title="Link to this heading"></a></h3>
|
||
<p>The examples below illustrate the approach to configuring the various
|
||
CPU models / features in QEMU and libvirt.</p>
|
||
<section id="qemu-command-line">
|
||
<h4>QEMU command line<a class="headerlink" href="#qemu-command-line" title="Link to this heading"></a></h4>
|
||
<p>Host passthrough:</p>
|
||
<pre class="literal-block">qemu-system-x86_64 -cpu host</pre>
|
||
<p>Host passthrough with feature customization:</p>
|
||
<pre class="literal-block">qemu-system-x86_64 -cpu host,vmx=off,...</pre>
|
||
<p>Named CPU models:</p>
|
||
<pre class="literal-block">qemu-system-x86_64 -cpu Westmere</pre>
|
||
<p>Named CPU models with feature customization:</p>
|
||
<pre class="literal-block">qemu-system-x86_64 -cpu Westmere,pcid=on,...</pre>
|
||
</section>
|
||
<section id="libvirt-guest-xml">
|
||
<h4>Libvirt guest XML<a class="headerlink" href="#libvirt-guest-xml" title="Link to this heading"></a></h4>
|
||
<p>Host passthrough:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'host-passthrough'</span><span class="o">/></span>
|
||
</pre></div>
|
||
</div>
|
||
<p>Host passthrough with feature customization:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'host-passthrough'</span><span class="o">></span>
|
||
<span class="o"><</span><span class="n">feature</span> <span class="n">name</span><span class="o">=</span><span class="s2">"vmx"</span> <span class="n">policy</span><span class="o">=</span><span class="s2">"disable"</span><span class="o">/></span>
|
||
<span class="o">...</span>
|
||
<span class="o"></</span><span class="n">cpu</span><span class="o">></span>
|
||
</pre></div>
|
||
</div>
|
||
<p>Host model:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'host-model'</span><span class="o">/></span>
|
||
</pre></div>
|
||
</div>
|
||
<p>Host model with feature customization:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'host-model'</span><span class="o">></span>
|
||
<span class="o"><</span><span class="n">feature</span> <span class="n">name</span><span class="o">=</span><span class="s2">"vmx"</span> <span class="n">policy</span><span class="o">=</span><span class="s2">"disable"</span><span class="o">/></span>
|
||
<span class="o">...</span>
|
||
<span class="o"></</span><span class="n">cpu</span><span class="o">></span>
|
||
</pre></div>
|
||
</div>
|
||
<p>Named model:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'custom'</span><span class="o">></span>
|
||
<span class="o"><</span><span class="n">model</span> <span class="n">name</span><span class="o">=</span><span class="s2">"Westmere"</span><span class="o">/></span>
|
||
<span class="o"></</span><span class="n">cpu</span><span class="o">></span>
|
||
</pre></div>
|
||
</div>
|
||
<p>Named model with feature customization:</p>
|
||
<div class="highlight-default notranslate"><div class="highlight"><pre><span></span><span class="o"><</span><span class="n">cpu</span> <span class="n">mode</span><span class="o">=</span><span class="s1">'custom'</span><span class="o">></span>
|
||
<span class="o"><</span><span class="n">model</span> <span class="n">name</span><span class="o">=</span><span class="s2">"Westmere"</span><span class="o">/></span>
|
||
<span class="o"><</span><span class="n">feature</span> <span class="n">name</span><span class="o">=</span><span class="s2">"pcid"</span> <span class="n">policy</span><span class="o">=</span><span class="s2">"require"</span><span class="o">/></span>
|
||
<span class="o">...</span>
|
||
<span class="o"></</span><span class="n">cpu</span><span class="o">></span>
|
||
</pre></div>
|
||
</div>
|
||
<section id="supported-cpu-model-configurations-on-mips-hosts">
|
||
<h5>Supported CPU model configurations on MIPS hosts<a class="headerlink" href="#supported-cpu-model-configurations-on-mips-hosts" title="Link to this heading"></a></h5>
|
||
<p>QEMU supports variety of MIPS CPU models:</p>
|
||
</section>
|
||
</section>
|
||
<section id="supported-cpu-models-for-mips32-hosts">
|
||
<h4>Supported CPU models for MIPS32 hosts<a class="headerlink" href="#supported-cpu-models-for-mips32-hosts" title="Link to this heading"></a></h4>
|
||
<p>The following CPU models are supported for use on MIPS32 hosts.
|
||
Administrators / applications are recommended to use the CPU model that
|
||
matches the generation of the host CPUs in use. In a deployment with a
|
||
mixture of host CPU models between machines, if live migration
|
||
compatibility is required, use the newest CPU model that is compatible
|
||
across all desired hosts.</p>
|
||
<dl class="simple">
|
||
<dt><code class="docutils literal notranslate"><span class="pre">mips32r6-generic</span></code></dt><dd><p>MIPS32 Processor (Release 6, 2015)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">P5600</span></code></dt><dd><p>MIPS32 Processor (P5600, 2014)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">M14K</span></code>, <code class="docutils literal notranslate"><span class="pre">M14Kc</span></code></dt><dd><p>MIPS32 Processor (M14K, 2009)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">74Kf</span></code></dt><dd><p>MIPS32 Processor (74K, 2007)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">34Kf</span></code></dt><dd><p>MIPS32 Processor (34K, 2006)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">24Kc</span></code>, <code class="docutils literal notranslate"><span class="pre">24KEc</span></code>, <code class="docutils literal notranslate"><span class="pre">24Kf</span></code></dt><dd><p>MIPS32 Processor (24K, 2003)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">4Kc</span></code>, <code class="docutils literal notranslate"><span class="pre">4Km</span></code>, <code class="docutils literal notranslate"><span class="pre">4KEcR1</span></code>, <code class="docutils literal notranslate"><span class="pre">4KEmR1</span></code>, <code class="docutils literal notranslate"><span class="pre">4KEc</span></code>, <code class="docutils literal notranslate"><span class="pre">4KEm</span></code></dt><dd><p>MIPS32 Processor (4K, 1999)</p>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
<section id="supported-cpu-models-for-mips64-hosts">
|
||
<h4>Supported CPU models for MIPS64 hosts<a class="headerlink" href="#supported-cpu-models-for-mips64-hosts" title="Link to this heading"></a></h4>
|
||
<p>The following CPU models are supported for use on MIPS64 hosts.
|
||
Administrators / applications are recommended to use the CPU model that
|
||
matches the generation of the host CPUs in use. In a deployment with a
|
||
mixture of host CPU models between machines, if live migration
|
||
compatibility is required, use the newest CPU model that is compatible
|
||
across all desired hosts.</p>
|
||
<dl class="simple">
|
||
<dt><code class="docutils literal notranslate"><span class="pre">I6400</span></code></dt><dd><p>MIPS64 Processor (Release 6, 2014)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Loongson-2E</span></code></dt><dd><p>MIPS64 Processor (Loongson 2, 2006)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Loongson-2F</span></code></dt><dd><p>MIPS64 Processor (Loongson 2, 2008)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Loongson-3A1000</span></code></dt><dd><p>MIPS64 Processor (Loongson 3, 2010)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">Loongson-3A4000</span></code></dt><dd><p>MIPS64 Processor (Loongson 3, 2018)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">mips64dspr2</span></code></dt><dd><p>MIPS64 Processor (Release 2, 2006)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">MIPS64R2-generic</span></code>, <code class="docutils literal notranslate"><span class="pre">5KEc</span></code>, <code class="docutils literal notranslate"><span class="pre">5KEf</span></code></dt><dd><p>MIPS64 Processor (Release 2, 2002)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">20Kc</span></code></dt><dd><p>MIPS64 Processor (20K, 2000</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">5Kc</span></code>, <code class="docutils literal notranslate"><span class="pre">5Kf</span></code></dt><dd><p>MIPS64 Processor (5K, 1999)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">VR5432</span></code></dt><dd><p>MIPS64 Processor (VR, 1998)</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">R4000</span></code></dt><dd><p>MIPS64 Processor (MIPS III, 1991)</p>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
<section id="supported-cpu-models-for-nanomips-hosts">
|
||
<h4>Supported CPU models for nanoMIPS hosts<a class="headerlink" href="#supported-cpu-models-for-nanomips-hosts" title="Link to this heading"></a></h4>
|
||
<p>The following CPU models are supported for use on nanoMIPS hosts.
|
||
Administrators / applications are recommended to use the CPU model that
|
||
matches the generation of the host CPUs in use. In a deployment with a
|
||
mixture of host CPU models between machines, if live migration
|
||
compatibility is required, use the newest CPU model that is compatible
|
||
across all desired hosts.</p>
|
||
<dl class="simple">
|
||
<dt><code class="docutils literal notranslate"><span class="pre">I7200</span></code></dt><dd><p>MIPS I7200 (nanoMIPS, 2018)</p>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
<section id="preferred-cpu-models-for-mips-hosts">
|
||
<h4>Preferred CPU models for MIPS hosts<a class="headerlink" href="#preferred-cpu-models-for-mips-hosts" title="Link to this heading"></a></h4>
|
||
<p>The following CPU models are preferred for use on different MIPS hosts:</p>
|
||
<dl class="simple">
|
||
<dt><code class="docutils literal notranslate"><span class="pre">MIPS</span> <span class="pre">III</span></code></dt><dd><p>R4000</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">MIPS32R2</span></code></dt><dd><p>34Kf</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">MIPS64R6</span></code></dt><dd><p>I6400</p>
|
||
</dd>
|
||
<dt><code class="docutils literal notranslate"><span class="pre">nanoMIPS</span></code></dt><dd><p>I7200</p>
|
||
</dd>
|
||
</dl>
|
||
</section>
|
||
</section>
|
||
</section>
|
||
<section id="see-also">
|
||
<h2>See also<a class="headerlink" href="#see-also" title="Link to this heading"></a></h2>
|
||
<p>The HTML documentation of QEMU for more precise information and Linux user mode emulator invocation.</p>
|
||
</section>
|
||
</section>
|
||
|
||
|
||
</div>
|
||
</div>
|
||
<footer>
|
||
|
||
<hr/>
|
||
|
||
<div role="contentinfo">
|
||
<p>© Copyright 2025, The QEMU Project Developers.</p>
|
||
</div>
|
||
|
||
Built with <a href="https://www.sphinx-doc.org/">Sphinx</a> using a
|
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|
||
provided by <a href="https://readthedocs.org">Read the Docs</a>.
|
||
|
||
|
||
<!-- Empty para to force a blank line after "Built with Sphinx ..." -->
|
||
<p></p>
|
||
|
||
<p>This documentation is for QEMU version 8.2.2.</p>
|
||
|
||
|
||
<p><a href="../about/license.html">QEMU and this manual are released under the
|
||
GNU General Public License, version 2.</a></p>
|
||
|
||
|
||
|
||
|
||
</footer>
|
||
</div>
|
||
</div>
|
||
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|
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|
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|
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